Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. Each programmable tile can include both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Although PLDs offer significant flexibility for implementing a wide range of application designs, there are constraints that must be followed when implementing a circuit design within a PLD. A “constraint” typically refers to a rule, or a set of rules, that specifies physical restrictions relating to the usage of programmable logic and/or programmable interconnect of a given PLD. These constraints dictate how the programmable logic and the programmable interconnect of the PLD may be used and/or configured when implementing a circuit design.
Software-based implementation tools, often referred to as Computer-Aided Design (CAD) tools, Electronic Design Automation (EDA) tools, or the like, follow these constraints when implementing a circuit design within a PLD. The implementation tools determine how the programmable logic and the programmable interconnect will be allocated and configured to implement the circuit design, while still observing the constraints.
The complexity of modern circuit designs and PLDs has led to the development of a multi-stage technique for implementing circuit designs within PLDs. In general, implementation tools have been built as a flow of multiple tasks, where each task is responsible for a specific portion of the overall implementation flow. For example, an implementation flow, sometimes referred to as a “CAD flow,” can include tasks such as synthesis, translation, packing, placement, and routing. Each of these tasks can be subdivided into further tasks, or sub-tasks. In this regard, a task such as placement can be broken down into a plurality of tasks and, therefore, can also be considered a CAD flow.
PLDs with new or enhanced architectures continually become available that can accommodate increasingly complex circuit designs. The constraints that must be followed when implementing a circuit design within a PLD change with the PLD architecture. That is, as the physical architecture of the PLD changes from one generation to the next, the constraints that must be observed also change. The implementation tools must be capable of following, or “handling,” these new constraints. Often, one or more tasks of the implementation flow cannot handle a new constraint and cannot easily be modified to do so.